This invention relates to a charge-coupled memory and, more particularly, relates to a charge-coupled line-addressable random-access memory (LARAM) which incorporates a uniphase clocking system.
The development of charge-coupled devices (CCD's) as described in the article by Gilbert F. Amelio, "Charge-Coupled Devices," Scientific American, Feb. 1974, Vol. 230, No. 2, p. 23, has made possible the fabrication of long shift registers having stages consisting of individual charge storage elements. These shift registers may be used in an interleaved format as in area-imaging devices or may be incorporated in analog delay lines. When strings of charge-coupled elements are organized in parallel format with associated addressing and date read-out circuitry, they become potentially suitable for use as random-access memories. This is true even though inherently such a collection of parallel shift registers does not allow random access to every bit in every register since the data in a given register must be circulated through a complete cycle to permit access to every bit. However, the circulation can be conducted at frequencies on the order of 5 to 10 MHz so the actual access time will be dependent only on line length and on clock frequency and will be on the order of microseconds, and access, as a practical matter, can be considered to be essentially random. Recirculating serial memories organized in parallel format have been reported to have, for example, 4096 bits of memory organized in 16 tracks of 256 bits each. See S. R. Rosenbaum and J. T. Caves, "CCD Memory Arrays with Fast Access by On-Chip Decoding," 1974 ISSCC Digest, pp. 210-211. The data continuously circulates in each track with the requirement that power be continuously supplied and with the result that the input/output circuitry must interact with a high capacitance since it has access to all lines at all times.
Charge-coupled shift registers may be designed with various clocking schemes. The most common and straight-forward schemes are four-phase, three-phase or two-phase schemes in which, respectively, every fourth, third or second electrode is tied to the same clock signal. The simplest scheme utilizes a single clock and is commonly denoted uniphase clocking. In this scheme, every second electrode is tied to the single clock while the alternating electrodes are held at a d.c. potential which lies inbetween the high and low extremes of the dynamic clock. In general, the simpler the clocking scheme, the higher the yield in fabricating the device and the more efficient the device in actual operation.